Two-level Pipelining of Systolic Array Graphics Engines

Abstract

In a systolic array, the maximum operating speed is determined by the most complex operation performed. In a systolic army graphics engine, capable of generating high quality images, one has to perform complex operations at a very high speed. We propose to use pipelined functional units in systolic army graphics engines as they can perform complex operations at high speeds. Due to time-varying discontinuities of operations performed by systolic army graphics engines, introduction of pipelined functional units is a complex problem. In this paper we present a methodology which solves this problem by a graph­ theoretic approach. Furthermore, we characterize the architectures which can be improved by pipelined functional units. Categories and Subject Descriptors: B.7.1 [Integrated Circuits}: Types and Design Styles VLSI C.l.1 [Single Data Stream Architectures}: Pipeline Processors C.S [Special-purpose and Application Based Systems}: Real-time Systems 1.3.1 [Computer Graphics]: Hardware Architecture - Raster Display Devices 1.3.7 [Computer Graphics]: Three-dimensional Graphics and Realism Color, Shading, Shadowing and Texture