EGGH: SIGGRAPH/Eurographics Workshop on Graphics Hardware: Recent submissions

Now showing items 301-320 of 524

    • The Graphics Unit of the INTEL 180860 

      Kursawe, Ulrich (The Eurographics Association, 1989)
      The Intel 180860 is a very powerful RISe processor, designed for applications that require a large amount of floating point and integer calculations. Additionally it supports graphics applications with a Graphics hardware ...

    • Viewing and Rendering Processor for a Volume Visualization System 

      Kaufman, A.; Bakalash, R.; Cohen, D. (The Eurographics Association, 1989)
      The architecture and the hardware realization of the 3D Viewing and Rendering Pro­ cessor is presented. This processor is a component of the Cube architecture, developed primarily for volume visualiza.tion. The processor ...

    • A Virtual Memory System Organization for Bit-Mapped Graphics Displays 

      Barkans, Anthony C. (The Eurographics Association, 1989)
      Described is a display sub-system, designed for support of a very high speed rendering engine. It provides high-performance graphics to an enVironment that consists of a hierarchy of resizable windows. The concept of virtual ...

    • Presentation of the Cubi9000: A Graphics System based on Inmos T800 Transputers 

      Glemot, France (The Eurographics Association, 1989)
      The Cubi9000 family includes a range of products from the 3D graphics terminal up to the 3D graphics workstation. The Cubi9000 when configured as a 3D graphics terminal connects to a host computer via a parallel interface ...

    • A Real-Time Raster Scan Display for 3-D Graphics 

      D.Jackèl,; Günther, H.; Herwig, B.; Rüsseler, H. (The Eurographics Association, 1989)
      This paper describes the architecture of a raster scan display for real-time visualisation of shaded polygons. A performance of 15-106 Phong shaded pixels per second is a primary goal of a pipelined rendering processor. ...

    • Two-level Pipelining of Systolic Array Graphics Engines 

      Jayasinghe, J. A. K. S.; Herrmann, O. E. (The Eurographics Association, 1989)
      In a systolic array, the maximum operating speed is determined by the most complex operation performed. In a systolic army graphics engine, capable of generating high quality images, one has to perform complex operations ...

    • A Dedicated Graphics Processor SIGHT-2 

      Yoshida, Masaharu; Naruse, Tadashi; Takahashi, Tokiichiro (The Eurographics Association, 1989)
      SIGHT-2 is a multiprocessor system that is intended to efficiently execute the ray tracing algorithm. To achieve high efficiency, three kinds of parallel execution mechanisms; (i) a multiprocessor configuration, (ii) a ...

    • A Generalised Parallel Architecture for Image Based Algorithms 

      Vaudin., G. J.; Nudd., G. R.; Atherton, T. J.; Clippingdale, S. C.; Francis., N. D.; Kerbyson., R.M. Howarth. D. J.; Packwood, R. A.; Walton, D. (The Eurographics Association, 1989)
      Real time image generation and image understanding require levels of computing power, that are beyond that available from conventional sequential machines. Current commercially available systems aimed at this area make use ...

    • VLSI Architecture for Anti-Aliasing 

      Romanova, Claudia; Wagner, Ulrich (The Eurographics Association, 1989)
      Computer-synthesized images exhibit the typical artifacts of raster displays, called alias­ ing, rastering, staircasing or the "jaggies". Display of an image on a raster CRT requires the sampling the two dimensional image ...

    • PS: Polygon Streams A Distributed Architecture for Incremental Computation Applied to Graphics 

      Gupta, Rajiv (The Eurographics Association, 1989)
      Polygon Streams is a distributed system with multiple processors a.nd strictly local communication. A unique custom VLSI chip that constitutes an independent processing module forms a stage of the PS pipeline. The number ...

    • The HERO Algorithm for Ray-Tracing Octrees 

      Agate, Mark; Grimsdale, Richard L.; Lister, Paul F. (The Eurographics Association, 1989)
      An algorithm is presented for rapid traversal of octree data structures, in order to enhance the speed of ray tracing for scenes of high complexity. At each level of the octree, the algorithm generates the addresses of ...

    • Towards a Taxonomy for Display Processors 

      Schneider, Bengt-Olaf (The Eurographics Association, 1989)
      Image generation for raster displays proceeds in two main steps: geometry processing and pixel processing. The snbsystem performing the pixel processing is called display processor.In the paper a model for the displa.y ...

    • A Hardware Algorithm for Fast Realistic Image Synthesis 

      Yilmaz, A. C.; Hagestein, S.; Deprettere, E.; Dewilde, P. (The Eurographics Association, 1989)
      A VLSI oriented algorithm, for the implementation of a generalized two-pass radiosity method is presented. The method allows any reflection behavior, varying from purely diffuse to perfect mirroring. Moreover, objects may ...

    • A VLSI Architecture for Image Composition 

      Shaw, Christopher D.; Green, Mark; Schaeffer, Jonathan (The Eurographics Association, 1988)
      This paper describes a new parallel architecture for performing high-speed raster graphics. A central host broadcasts graphical objects to a number of identical graphics processors. Each graphics processor produces a raster ...

    • Parallel Processing on a Transputer-based Graphics Board 

      Pereira, Joijo; Reis, Francisco; Vinagre, Carlos; Gomes, Mario R. (The Eurographics Association, 1988)
      Th.s paper discusses the design of a graphics board with parallel architecture based on Transputers and a resolution of 1024 x 1024 x 8 [VIN88], namely: Ihe processing unit (il plays the role of a display processor), the ...

    • Combining Z-buffer Engines for Higher-Speed Rendering 

      Molnar, Steven (The Eurographics Association, 1988)
      Described IS a hardware architecture for combining the outputs of a number of z-buffer rendering engines to achieve higher performance than is possible with a single renderer. It allows a combination of renderers to achieve ...

    • The voxblt Engine: A Voxel Frame Buffer Processor 

      Kaufman, Arie (The Eurographics Association, 1988)
      The voxblt Engine (vE) is a 3D frame-buffer processor which manipulates and processes ''3~ bitmaps"" (voxel maps) stored in a cubic frame buffer of voxels. The vE is the 3D counterpart of the 20 frame buffer processor, ...

    • Hardware Support for the Display and Manipulation of Binary Voxel Models 

      Jense, G.J.; Huijsmans, D.P. (The Eurographics Association, 1988)
      We describe some of our experiences with the implementation of a 3D reconstruction system for the visualization of the shapes and structural development of biological objects. We use a binary voxel model as volumetric ...

    • "A Display Controller for an Object-levelFrame Store System" 

      Jayasinghe, JAK.S.; Kuijk, A.A.M.; Spaanenburg, L. (The Eurographics Association, 1988)
      In [3] and [1] a new architecture for a Computer Image Generating (CIG) system designed to have optimal interaction support for realistic 3D graphics has been presented. There it was stated that from an interaction paint ...

    • PROOF: An Architecture for Rendering In Object Space 

      Schneider, Bengt-Olaf; Claussen, Ute (The Eurographics Association, 1988)
      This paper gives a short introduction into the field of computer image generation in hardware. It discusses the two main approaches, namely partitioning in Image space and In object space. Based on the object space ...