| dc.contributor.author | Smit, J. | en_US |
| dc.contributor.author | Wessels, N.J. | en_US |
| dc.contributor.author | Horst, A. van del' | en_US |
| dc.contributor.author | Bentum, M.J. | en_US |
| dc.contributor.editor | P F Lister | en_US |
| dc.date.accessioned | 2014-02-06T14:19:41Z | |
| dc.date.available | 2014-02-06T14:19:41Z | |
| dc.date.issued | 1992 | en_US |
| dc.identifier.isbn | - | en_US |
| dc.identifier.issn | - | en_US |
| dc.identifier.uri | http://dx.doi.org/10.2312/EGGH/EGGH92/070-076 | en_US |
| dc.description.abstract | An architecture for a Real-Time Volume Rendering Engine is given capable of computing750x750x512 samples from a 3D dataset at a rate of 25 images per second.The RT-VRE uses for this purpose 64 dedicated rendering chips, cooperating with 16RISe-processors. An plane interpolator circuit and a composition circuit, both capableto operate at very high speeds, have been designed for a 1.6 micron VLSI process.The interpolator is now back from production. It has been tested an complied withour specifications." | en_US |
| dc.publisher | The Eurographics Association | en_US |
| dc.title | On the Design of a Real-Time Volume Rendering Engine | en_US |
| dc.description.seriesinformation | Eurographics Workshop on Graphics Hardware | en_US |
