On the Design of a Real-Time Volume Rendering Engine
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1992Pay-Per-View via TIB Hannover:
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An architecture for a Real-Time Volume Rendering Engine is given capable of computing750x750x512 samples from a 3D dataset at a rate of 25 images per second.The RT-VRE uses for this purpose 64 dedicated rendering chips, cooperating with 16RISe-processors. An plane interpolator circuit and a composition circuit, both capableto operate at very high speeds, have been designed for a 1.6 micron VLSI process.The interpolator is now back from production. It has been tested an complied withour specifications."
BibTeX
@inproceedings {10.2312:EGGH:EGGH92:070-076,
booktitle = {Eurographics Workshop on Graphics Hardware},
editor = {P F Lister},
title = {{On the Design of a Real-Time Volume Rendering Engine}},
author = {Smit, J. and Wessels, N.J. and Horst, A. van del' and Bentum, M.J.},
year = {1992},
publisher = {The Eurographics Association},
ISSN = {-},
ISBN = {-},
DOI = {10.2312/EGGH/EGGH92/070-076}
}
booktitle = {Eurographics Workshop on Graphics Hardware},
editor = {P F Lister},
title = {{On the Design of a Real-Time Volume Rendering Engine}},
author = {Smit, J. and Wessels, N.J. and Horst, A. van del' and Bentum, M.J.},
year = {1992},
publisher = {The Eurographics Association},
ISSN = {-},
ISBN = {-},
DOI = {10.2312/EGGH/EGGH92/070-076}
}