dc.contributor.author | Anson, R. C. | en_US |
dc.contributor.author | Tweedly, A. G. | en_US |
dc.contributor.editor | D. S. Greenaway and E. A. Warman | en_US |
dc.date.accessioned | 2015-09-29T08:28:45Z | |
dc.date.available | 2015-09-29T08:28:45Z | |
dc.date.issued | 1982 | en_US |
dc.identifier.issn | 1017-4656 | en_US |
dc.identifier.uri | http://dx.doi.org/10.2312/eg.19821023 | en_US |
dc.description.abstract | To meet the variety of layout challenges raised by developing VLSI technology, a new Autolayout system has been developed. This flexible tool provides automated or interactive layout of both 'mass-production' and custom logic IC's for a variety of MOS technologies. The layout process accommodates 2 or 3 routing layers, signals of different widths and produces power and ground connections entirely on a single layer. Additionally the system allows its algorithms to be controlled and directed so that it can be highly tuned to a particular application. The system is integrated with other Integrated Circuit Design aids such as GAELIC, TARTAN and CHECK. | en_US |
dc.publisher | The Eurographics Association | en_US |
dc.title | ALITE - AN ENGINEERING TOOL FOR AUTOMATIC CHIP DESIGN | en_US |
dc.description.seriesinformation | Eurographics Conference Proceedings | en_US |
dc.identifier.doi | 10.2312/eg.19821023 | en_US |