VLSI Drawing Processor Utilizing Multiple ParallelScan-Line Processors

Abstract

In a typical graphics system, a single drawing processor is used to perform pixel level drawing operations, one pixel at a time. A VLSI based drawing processor and image memory controller is presented which takes advantage of scan-line partitioning of many graphics operations. A four processor implementation is described which operates on four scan-lines in parallel to achieve near real-time shading performance for complex objects. Drawing processor commands are provided for points, vectors, triangles, rectangles, block pixel moves, and image transfers. Vectors and triangles can be drawn with shading and depth buffering. The chips also incorporate integral vector and area pattern registers, and support translucency. The drawing processor chips directly interface to the image memory RAMs without any external buffers, registers, caches, or control logic, allowing a high performance system to be configured simply and cost effectively. These chips are implemented in the GX4000 high performance workstation graphics system which is capable of rendering close to 200,000 shaded and depth-buffered 100 pixel polygons per second and over 34,000 shaded and depth-buffered 1000 pixel polygons per second.