dc.contributor.author | Owens, John D. | en_US |
dc.contributor.author | Dally, William J. | en_US |
dc.contributor.author | Kapasi, Ujval J. | en_US |
dc.contributor.author | Rixner, Scott | en_US |
dc.contributor.author | Mattson, Peter | en_US |
dc.contributor.author | Mowery, Ben | en_US |
dc.contributor.editor | I. Buck and G. Humphreys and P. Hanrahan | en_US |
dc.date.accessioned | 2013-10-28T09:57:02Z | |
dc.date.available | 2013-10-28T09:57:02Z | |
dc.date.issued | 2000 | en_US |
dc.identifier.isbn | 1-58113-257-3 | en_US |
dc.identifier.issn | 1727-3471 | en_US |
dc.identifier.uri | http://dx.doi.org/10.2312/EGGH/EGGH00/023-032 | en_US |
dc.description.abstract | The use of a programmable stream architecture in polygon rendering provides a powerful mechanism to address the high performance needs of today s complex scenes as well as the need for flexibility and programmability in the polygon rendering pipeline. We describe how a polygon rendering pipeline maps into data streams and kernels that operate on streams, and how this mapping is used to implement the polygon rendering pipeline on Imagine, a programmable stream processor. We compare our results on a cycleaccurate simulation of Imagine to representative hardware and software renderers. | en_US |
dc.publisher | The Eurographics Association | en_US |
dc.subject | I.3.1 [Computer Graphics] | en_US |
dc.subject | Hardware Architecture Graphics Processors C.1.2 [Processor Architectures] | en_US |
dc.subject | Multiple Data Stream Architectures Single | en_US |
dc.subject | instructionstream | en_US |
dc.subject | multiple | en_US |
dc.subject | data | en_US |
dc.subject | stream processors (SIMD) | en_US |
dc.title | Polygon Rendering on a Stream Architecture | en_US |
dc.description.seriesinformation | SIGGRAPH/Eurographics Workshop on Graphics Hardware | en_US |