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dc.contributor.authorKeely, Seanen_US
dc.contributor.editorIngo Wald and Jonathan Ragan-Kelleyen_US
dc.date.accessioned2015-07-06T15:26:31Z
dc.date.available2015-07-06T15:26:31Z
dc.date.issued2014en_US
dc.identifier.isbn978-3-905674-60-6en_US
dc.identifier.issn2079-8679en_US
dc.identifier.urihttp://dx.doi.org/10.2312/hpg.20141091en_US
dc.identifier.urihttps://diglib.eg.org:443/handle/10.2312/hpg.20141091
dc.description.abstractWe propose a high performance, GPU integrated, hardware ray tracing system. We present and make use of a new analysis of ray traversal in axis aligned bounding volume hierarchies. This analysis enables compact traversal hardware through the use of reduced precision arithmetic. We also propose a new cache based technique for scheduling ray traversal. With the addition of our compact fixed function traversal unit and cache mechanism, we show that current GPU architectures are well suited for hardware accelerated ray tracing, requiring only small modifications to provide high performance. By making use of existing GPU resources we are able to keep all rays and scheduling traffic on chip and out of caches. We used simulations to estimate the performance of our architecture. Our system achieves an average ray rate of 3.4 billion rays per second while path tracing our test scenes.en_US
dc.publisherThe Eurographics Associationen_US
dc.subjectI.3.1 [Computer Graphics]en_US
dc.subjectHardware Architectureen_US
dc.subjectGraphics processorsen_US
dc.subjectI.3.7 [Computer Graphics]en_US
dc.subjectThree Dimensional Graphics and Realismen_US
dc.subjectRaytracingen_US
dc.titleReduced Precision for Hardware Ray Tracing in GPUsen_US
dc.description.seriesinformationEurographics/ ACM SIGGRAPH Symposium on High Performance Graphicsen_US


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