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dc.contributor.authorPotmesil, Michaelen_US
dc.contributor.authorMcMillan, Leonarden_US
dc.contributor.authorHoffert, Eric M.en_US
dc.contributor.authorInman, Jennifer F.en_US
dc.contributor.authorFarah, Robert L.en_US
dc.contributor.authorHoward, Marcen_US
dc.date.accessioned2015-10-05T07:56:08Z
dc.date.available2015-10-05T07:56:08Z
dc.date.issued1989en_US
dc.identifier.issn1017-4656en_US
dc.identifier.urihttp://dx.doi.org/10.2312/egtp.19891014en_US
dc.description.abstractWe describe the system architecture and the programming environment of the Pixel Machine - a parallel image computer for 2D and 3D image synthesis and analysis. The architecture of the computer is based on an array of asynchronous MIMD nodes with a parallel access to a large frame buffer. The system consists of a pipeline of pipe nodes which execute sequential algorithms and an array of m x n pixel nodes which execute parallel algorithms. A pixel node accesses every m-th pixel on every n-th scan line of a distributed frame buffer. Each processing node is based on a high-speed, floating-point programmable processor. The programmability of the computer allows all algorithms to be implemented in software. A set of mapping functions transfers image algorithms written for conventional single-processor computers to algorithms which execute in the pixel nodes and access the distributed frame buffer. The ability to use floating-point computations in pixel operations, such as antialiasing, ray tracing, and filtering, allows high-quality image generation and processing. The image computer provides up to 820 megaflops of peak processing power and 48 megabytes of memory for data-visualization applications.en_US
dc.publisherEurographics Associationen_US
dc.titleA Parallel Image Computer with a Distributed Frame Buffer: System Architecture and Programmingen_US
dc.description.seriesinformationEG 1989-Technical Papersen_US
dc.identifier.doi10.2312/egtp.19891014en_US


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