dc.contributor.author | Wei, Bin | en_US |
dc.contributor.author | Clark, Douglas W. | en_US |
dc.contributor.author | Felten, Edward W. | en_US |
dc.contributor.author | Li, Kai | en_US |
dc.contributor.editor | S. N. Spencer | en_US |
dc.date.accessioned | 2014-02-06T15:01:27Z | |
dc.date.available | 2014-02-06T15:01:27Z | |
dc.date.issued | 1998 | en_US |
dc.identifier.isbn | 0-89791-097-X | en_US |
dc.identifier.issn | 1727-3471 | en_US |
dc.identifier.uri | http://dx.doi.org/10.2312/EGGH/EGGH98/087-096 | en_US |
dc.description.abstract | A multiple-port, distributed frame buffer has been recently proposed to support parallel rendering on multicomputers. This paper describes an implementation of such a distributed frame buffer for the Intel Paragon routing network, and reports its performance results. We have conducted several experiments with the system we have developed. Our results indicate that placing a multipleport, distributed frame buffer directly on the host internal routing network can provide high throughput to eliminate the bottleneck of merging a final image from multiple processors to a frame buffer. This architectural approach can also effectively support image composition for sort-last. The synchronization algorithm we have developed requires only one-way communication and minimizes receive overhead for message passing to the frame buffer. | en_US |
dc.publisher | The Eurographics Association | en_US |
dc.subject | B.4.3 [Input/Output] | en_US |
dc.subject | Subsystems | en_US |
dc.subject | Parallel I/O | en_US |
dc.subject | 1.3.1 [Computer Graphics] | en_US |
dc.subject | Hardware Architecture | en_US |
dc.subject | Parallel Processing | en_US |
dc.subject | C.4 [Performance of Systems] | en_US |
dc.subject | Design Studies. | en_US |
dc.title | Performance Issues of a Distributed Frame Buffer on a Multicomputer | en_US |
dc.description.seriesinformation | SIGGRAPH/Eurographics Workshop on Graphics Hardware | en_US |