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dc.contributor.authorRegan, Matthewen_US
dc.contributor.authorPose, Ronalden_US
dc.contributor.editorW. Strasseren_US
dc.date.accessioned2014-02-06T14:27:10Z
dc.date.available2014-02-06T14:27:10Z
dc.date.issued1994en_US
dc.identifier.isbn-en_US
dc.identifier.issn-en_US
dc.identifier.urihttp://dx.doi.org/10.2312/EGGH/EGGH94/023-027en_US
dc.description.abstractAn address recalculation pipeline used in conjunction with image composition enables the profitable technique of prioritized rendering to be employed in virtual reality applications. These techniques however require the use of large amounts of fast static memory. Aliasing is also introduced in the system and must be removed with special anti-aliasing hardware. The demands on the display memory are quite severe and an unusual memory architecture and addressing scheme are employed to meet those demands. This results in the required performance and excellent memory efficiency while requiring relatively few components. The system provides far better performance at a lower cost than high-end conventional graphics computer systems running virtual reality applications.en_US
dc.publisherThe Eurographics Associationen_US
dc.titleDisplay Memory Access Issues and Anti-Aliasing with a Virtual Reality Graphics Controller.en_US
dc.description.seriesinformationEurographics Workshop on Graphics Hardwareen_US


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