| dc.contributor.author | Vijt, P De | en_US |
| dc.contributor.author | Claesen, L | en_US |
| dc.contributor.author | Man, H De | en_US |
| dc.contributor.editor | P. F. Lister and R. L. Grimsdale | en_US |
| dc.date.accessioned | 2014-02-06T14:24:18Z | |
| dc.date.available | 2014-02-06T14:24:18Z | |
| dc.date.issued | 1993 | en_US |
| dc.identifier.isbn | - | en_US |
| dc.identifier.issn | - | en_US |
| dc.identifier.uri | http://dx.doi.org/10.2312/EGGH/EGGH93/093-112 | en_US |
| dc.description.abstract | A new fast ray - patch intersection algorithm is presented. The algorithm correctly handles all ray - patch intersections. A number of parametersare derived from a numerical analysis of the algorithm and the datapad is re synthesized for higher accuracy. A global architecture for anASIC for intersecting a ray with a bezier patch is presented. It is shownthat a cache combined with pre pads can reduce the required memory considerablewith an extremely small performance penalty. Attention will bepaid to the scheduling and control problem. Several high level optimizationsare presented that make efficient scheduling possible and decreasethe calculation time considerably. | en_US |
| dc.publisher | The Eurographics Association | en_US |
| dc.title | An Architecture for Ray - Bezier Patch Intersection | en_US |
| dc.description.seriesinformation | Eurographics Workshop on Graphics Hardware | en_US |
