Improving BVH Ray Tracing Speed Using the AVX Instruction Set

Abstract

High performance ray tracing on the CPU requires the efficient utilization of SIMD instructions. Ray packet and ray stream traversal algorithms achieve this by performing computations on multiple rays, nodes, or primitives at the same time. In this paper, we present our approach to optimizing coherent BVH ray packet tracing for the new AVX instruction set, which enables 8-wide SIMD operations on 32-bit floating-point numbers. We have measured an average speedup of about 50 percent compared to our SSE4.1 implementation, on an Intel Sandy Bridge processor.