This paper describes the Junctionality oj a 3D Graphics Raster Processor called TAYRA. TAYRA consists in the most part oj Graphics Raster Pipeline with five major external interfaces: PCI Master/Target, Depth, Texture, ...

This paper details the design o f an advanced 32 bit 3D frame buffer memory controller for a 3D Graphics Raster Processor called TAYRA [1]. This memory controller is designed to provide a performance o f 33 MPixelsls for ...